1. Field of the Invention
This invention relates to a program execution control system for the condition determination, conditional branch and condition execution process of a program for the processing unit of a computer.
2. Description of the Related Art
Conventionally, the condition processing in the processing unit is effected as follows. The processing unit stores the logical comparison or operation result in a single flag indicating zero, positive or negative. The processing unit uses a conditional branch instruction for branching when the flag satisfies a specified condition. Therefore, as shown in two examples (which are described by C language) of FIGS. 1A and 1B, an if-statement having the compound condition is executed, and the conditional branch must be repeatedly executed by sequentially comparing the individual conditions in order.
Recently, when the branch is executed in a computer of pipeline processing system usually used as the high-speed processing method, instructions read out and stored until the branching is started are made invalid as shown in FIG. 2. Further, in the above computer, readout of the branch destination instruction will be postponed until the branch destination address is created and made ready for readout. As described above, the branch instruction is a main factor which may disturb the flow of pipeline process and lower the processing performance in the general computer of pipeline processing system. In FIG. 2, F, D, E and W indicate respective processing stages in the pipeline processing feature. F indicates the instruction fetch stage, D indicates the decode stage, E indicates the execution stage, and W indicates the result writing stage. OP1 indicates an instruction generated immediately before the branch instruction. B indicates the branch instruction. OP2 and OP3 respectively indicate the instruction allocated immediately after the branch instruction, which is fetched by the instruction fetch stage and positioned thereafter discarded by the branching. OP4 indicates the instruction of a branch destination. OP5, OP6 and OP7 indicate the instructions executed after the instruction OP4. TD indicates the apparent process interruption time. TD' indicates a period of time from when the branching is recognized until the branch destination can be made ready for fetching.
As a method for solving the above problem, there is provided a delayed branch system for continuously effecting the pipeline process by arranging an instruction to execute before branch also in a cycle from the time immediately after the branch instruction is specified until the time immediately before the branch destination instruction is read out, that is, in a delayed-slot. However, it is difficult to arrange instructions in all the delayed-slots. Therefore, in the conventional processing system in which the branch instruction tends to frequently occur, problems that the performance is lowered by the branch instruction will frequently occur.
In the conventional system, since only one set of flags of comparison results or the like is used and the condition determination is effected by use of the branch instruction, the condition determination must be sequentially made. Thus, in a computer of parallel processing system capable of simultaneously executing a plurality of instructions, it is difficult to effect the condition processes in parallel.
The following method is provided to solve the above problem.
The result of comparison or the like can be stored into a desired general register and the results of individual conditions are previously stored into individual registers. After this, the condition determination for them is made. With this method, it is only required to use one branch and the possibility of the condition processes in parallel can be enhanced. However, in this system, valuable registers of a number corresponding to the number of conditions are necessary. Therefore, in this system, the efficiency of usage of the registers is lowered and consequently the frequency of the memory access becomes high, thereby lowering the performance. As a result, in this system, the effect that the number of branch instructions is decreased and the possibility of parallel process is enhanced can be attained, but a large number of bad side effects occur.
As described above, in the conventional program execution control system, firstly, when the branches such as "IF-ELSE IF- . . . ELSE" constructed by a plurality of conditions are compiled and executed, the conditional branch must be executed while checking individual conditions. Therefore, the code creation efficiency and execution speed cannot be enhanced. Secondly, since the number of branches tends to be increased, an influence of reduction in the processing speed due to disturbance and interruption of the pipeline in the branch is large in a computer of pipeline processing system. Thirdly, since the result of comparison instruction or the like is set into a flag at one place, the result of comparison made before another comparison is made is rewritten after the latter comparison is made and cannot be used. Therefore, simultaneous determination of the compound condition or parallel condition processing cannot be effected. Fourthly, in a computer in which the determination result of the register is saved, the efficiency of usage of the registers is low, thereby lowering the performance.